Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
In conventional flipchip type packages, a semiconductor die is mounted to a package substrate with the active side of the die facing the substrate. Conventionally, the interconnection of the circuitry in the semiconductor die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die and bonded to a corresponding complementary array of interconnect pads, often referred to as capture pads on the substrate.
The areal density of electronic features on integrated circuits has increased enormously, and a semiconductor die having a greater density of circuit features also may have a greater density of sites for interconnection with the package substrate.
The package is connected to underlying circuitry, such as a printed circuit board or motherboard, by way of second level interconnects between the package and underlying circuit. The second level interconnects have a greater pitch than the flipchip interconnects, and so the routing on the substrate conventionally fans out. Significant technological advances have enabled construction of fine lines and spaces. In the conventional arrangement, space between adjacent pads limits the number of traces than can escape from the more inward capture pads in the array. The fan-out routing between the capture pads beneath the semiconductor die and external pins of the package is formed on multiple metal layers within the package substrate. For a complex interconnect array, substrates having multiple layers can be required to achieve routing between the die pads and second level interconnects on the package.
Multiple layer substrates are expensive and, in conventional flipchip constructs, the substrate alone typically accounts for more than half the package cost. The high cost of multilayer substrates has been a factor in limiting proliferation of flipchip technology in mainstream products. The escape routing pattern typically introduces additional electrical parasitics because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.
In some conventional processes, a flipchip interconnect is made by contacting the bumps or balls on the semiconductor die with corresponding interconnect sites on the substrate circuitry, and then heating to reflow the fusible portion of the solder bumps or to reflow the solder bumps in their entirety to make the electrical connection. In such processes, the melted solder may flow from the interconnect site along the metal of the circuitry, depleting the solder at the connection site and, where the bumps are collapsible under reflow conditions, the bumps may contact adjacent circuitry or nearby bumps, resulting in electrical failure. To avoid these problems, the solder is confined by a solder mask formed as a layer of dielectric material overlying the patterned metal layer at the die mount surface of the substrate with an opening exposing an interconnect site on the underlying circuitry. Process limitations in patterning the solder mask prevent reliably forming well-aligned and consistently dimensioned openings and, accordingly, where a solder mask is employed, substrates having fine circuitry feature dimensions as would be required for finer pitch interconnection are not attainable.
The interconnect pitch in a conventional flipchip interconnect is limited in part by the dimensions of the capture pads on the substrate. The capture pads are typically much wider than the connecting circuit elements. Recently, flipchip substrate circuitry designs have been disclosed, in which reliable interconnection is made on narrow circuit elements on the substrate, as bond-on-narrow pad (BONP) interconnections described in U.S. patent publication 20060216860, and as bump-on-lead (BOL) interconnections described in U.S. patent publication 20050110164, both incorporated by reference. Where a conventional solder mask is employed, limitations in the process for patterning the solder mask can limit pitch reduction even in some BONP or BOL substrate configurations. The exposed bondable surface of the lead may be contaminated by or covered by solder mask residue, resulting in an imperfect solder joint. The bondable surface of the lead may be inconsistently or only partially exposed at the interconnect site, resulting in an unreliable and inconsistent trace structure.
The conventional flipchip interconnection is made by using a melting process to join the bumps onto mating surfaces of corresponding interconnect sites on the patterned metal layer at the die attach surface of the substrate. Where the site is a capture pad, the interconnect is known as a bump-on-capture pad (BOC) interconnect. Where the site is a lead or narrow pad, the interconnect is known as a BOL or BONP interconnect. In the BOC design, a comparatively large capture pad is required to mate with the bump on the semiconductor die. In some flipchip interconnections, an insulating material or solder mask is required to confine the flow of solder during the interconnection process. The solder mask opening defines the contour of the melted solder at the capture pad, i.e., solder mask defined, or the solder contour may not be defined by the mask opening, i.e., non-solder mask defined. In the latter case, the solder mask opening is significantly larger than the capture pad. Since the techniques for defining solder mask openings have wide tolerance ranges for a solder mask defined bump configuration, the capture pad must be large, typically considerably larger than the design size for the mask opening, to ensure that the mask opening is located on the mating surface of the pad. For a non-solder mask defined bump configuration, the solder mask opening must be larger than the capture pad. The width or diameter of capture pads can be as much as two to four times wider than the trace width. The larger width of the capture pads results in considerable loss of routing space on the top substrate layer. In particular, the escape routing pitch is much larger than the finest trace pitch that the substrate technology can offer. A significant number of pads must be routed on lower substrate layers by means of short stubs and vias, often beneath the footprint of the die, emanating from the pads in question.
FIGS. 1-3 show aspects of a conventional flipchip interconnection using a solder mask. FIG. 1 shows substrate 12 in a diagrammatic sectional view or plan view taken in a plane parallel to the substrate surface. Certain features are shown as if transparent. Substrate 12 includes a dielectric layer, supporting a metal layer at the die attach surface, patterned to form circuitry underlying the solder mask. The circuitry includes leads or traces 15 exposed at interconnect sites 19 by openings 18 in solder mask 16, as shown in FIG. 2. The conventional solder mask can have a nominal mask opening diameter in the range of 80 to 90 micrometers (μm). Solder mask materials can be resolved at such pitches and, particularly, substrates can be made comparatively inexpensively with solder masks having 90 μm openings and alignment tolerances plus or minus 25 μm. In some embodiments, laminate substrates made according to standard design rules, such as 4-metal layer laminates, are used. Traces 15 have a 90 μm pitch and the narrow pads are located in a 270 μm area array providing an effective escape pitch about 90 μm across the edge of the die footprint, indicated by broken line 11.
In FIG. 3, the interconnection of semiconductor die 34 onto substrate 12 is achieved by mating bumps 35 directly onto interconnect sites 19 on narrow leads or traces 15 patterned on a dielectric layer on the die attach surface of substrate 12. In this example there is no pad, and solder mask 16 serves to limit flow of solder within the bounds of mask openings 18, preventing solder flow away from the interconnect site along the solder-wettable lead. The solder mask also confines flow of molten solder between leads in the course of the assembly process. However, the density of flipchip interconnection in which a solder mask is desired is limited by process capability of the solder mask patterning process.
An underfill material 37 between the active side of semiconductor die 34 and solder mask 16 over substrate 12 protects the interconnections and mechanically stabilizes the assembly. Underfill material 37 can be a curable resin plus a filler, which is typically a fine particulate material such as silica or alumina particles. The particular resin and filler, as well as the proportion of filler in the resin, are selected to provide suitable mechanical and adhesion properties to underfill material 37, both during processing and in the resulting underfill. Underfill material 37 is formed after the interconnection has been made between interconnect sites 19 on substrate 12 and bumps 35 on semiconductor die 34 by applying the underfill material in a liquid form to the narrow space between the die and substrate near an edge of the die. Underfill material 37 is permitted to flow by capillary action into the space, referred to as capillary underfill. Alternatively, underfill material 37 is deposited by applying a quantity of the underfill material to the active side of semiconductor die 34 or to solder mask 16 over substrate 12, then moving the die toward the substrate and pressing bumps 35 against interconnect sites 19, referred to as no-flow underfill.
FIGS. 4 and 5 show aspects of a conventional flipchip interconnection without using a solder mask. FIG. 4 shows a package assembly, in a diagrammatic partial sectional view taken in a plane parallel to the substrate surface, along the lines 4-4′ in FIG. 5. Certain features are shown as if transparent. FIG. 5 shows a partial sectional view of a package as in FIG. 4, taken in a plane perpendicular to the plane of the package substrate surface, along line 5-5′ in FIG. 4.
FIG. 4 shows an escape routing pattern for substrate 42 arranged for the semiconductor die on which the die attach pads are located in an array of parallel rows near the die perimeter. The patterned traces or leads 43 are routed according to a pattern complementary to the arrangement of bumps 45 on the semiconductor die. The BOL interconnection is achieved by mating bumps 45 directly onto respective interconnect sites 40 of narrow leads or traces 43 on substrate 42 in a complementary array near the edge of the die footprint, indicated by broken line 41. The leads 43 are formed by patterning a metal layer on a die attach surface of substrate dielectric layer 42. The electrical interconnection of semiconductor die 46 is made by joining bumps 45 formed on interconnect pads on the active side of the die onto interconnect sites 40, as shown in FIG. 5. Certain ones of escape traces 43 pass between bumps 45 and are routed across substrate 42 in rows toward the interior of the die footprint.
Without a solder mask, the molten bump material can be confined by a non-collapsible bump with solder on the interconnect site. Alternatively, an encapsulating resin adhesive is employed in a no-flow underfill process to confine the solder flow during the melt phase of the interconnection process. The no-flow underfill material is applied before semiconductor die 46 and substrate 42 are brought together. The no-flow underfill material is displaced by the approach of bumps 45 onto interconnect sites 40, and by the opposed surfaces of the die and the substrate. The adhesive for the no-flow underfill material can be a fast-gelling adhesive or other material that gels sufficiently at the gel temperature in a time period in the order of 1-2 seconds.